LXT6155LE datasheet(30/50 Pages) INTEL

30 / 50 page

LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver

Datasheet

Table 17. Rx PLL 2, Register #9 (Address A<3:0>=1001)

Bit

Default

Mnemonic

Description

Not for customer use

5:3

0.1.1

freq_det_pw

Frequency detector output pulse width ({1 to 8} * 6.43 ns)

Not for customer use

Table 18. Test, Register #10 (Address A<3:0>=1010)

Bit

Default

Mnemonic

Description

los_clk_ena

Enables Rx clock switching under LOS/LOCK condition:

0 = disable

1 = enable

Not for customer use

5:2

0.0.0.0

Not for customer use

Table 19. Register, Bias and Fuse Controls, Register #11 (Address A<3:0>=1011)

Bit

Default

Mnemonic

Description

bias_pwrdn

Power down all bias generators. This bit can be used to power down all the active

analog circuitry on the device.

0= active

1=power down

reg_reset

write only.

5:2

1.0.0.0

Not for customer use

1:0

0.0

Not for customer use

Table 20. Rx Digital 1, Register #12 (Address A<3:0>=1100)

Bit

Default

Mnemonic

Description

los_format

Combine (logical OR) LOS/LOCK function onto LOS pin:

0 = disable

1 = enable

los_amp_trim

Amplitude LOS threshold trim:

0 = Reduced ALOS dessert threshold (-3db)

1 = Nominal ALOS thresholds

LXT6155LE Datasheet(PDF) 30 Page - Intel Corporation

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