LXT6155LE datasheet(20/50 Pages) INTEL

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LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver

Datasheet

2.5.1

Hardware Mode

By setting HWSEL = Low, the LXT6155 operates in standalone hardware mode, without a serial

microprocessor interface. A subset of the functions available in the Software Mode can be set in

Hardware Mode. LXT6155 provides a comprehensive flexibility in configuring system clock

preference settings, as well as providing pins for activating loopback test modes. Tables 3, 4 and 5

show the settings that enable the functions available in hardware mode.

Figure 7. Hardware Mode

2.5.1.1

PLL Clock Reference (CIS pin)

The reference clock plays two roles: it centers the receive PLL, and it provides the receive output

clocks RSOCLKP/RSOCKLN and RPOCLK in case of Loss of Signal. When the LXT6155

powers up, it looks for this reference clock to start-up internal blocks, including the receive PLL

circuitry.

2.5.1.1.1

TICLK

This is the transmit input clock(s): either TSICLKP/TSICLKN in serial mode or TPICLK in

parallel mode.

2.5.1.1.2

XTAL

XTAL is an optional clock, created using an external crystal, connected across the XTALIN and

XTALOUT pins. The crystal provides an independent and stable clock source. This clock is also

used as the reference for the Tx clock monitoring circuitry.

Nevada

HWSEL

RLIS

CIS

GND

Remote loopback

Serial/Parallel

Clock reference select

Local loopback

LLIS

MODE

Line interface encode/

decode

RIFE

Frame Enable

Table 3.

Reference Clock Settings

CIS

Clock Reference

Note

Low

TICLK

Default mode. The LXT6155 uses the transmit input clock as the

reference clock for on chip operations. No crystal is needed.

High

XTAL

The LXT6155 uses the clock signal at XTALIN as the reference

clock for Rx operation. This can either be an applied 19.44MHz

clock or a 19.44MHz crystal can be connected across XTALIN &

XTALOUT. See Table 24 for the crystal specifications.

1. For explanation, see clock sections below.

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