LXT6155LE datasheet(40/50 Pages) INTEL

40 / 50 page

LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver

Datasheet

Figure 20. Receive Serial Output Data Timing (See Table 30)

Figure 21. Receive Parallel Output Data Timing (See Table 30)

Reference Clock Offset from

Nominal

-100

100

ppm

Table 30. Receive Timing Characteristics (See Figures 20 and 21) (Continued)

Parameter

Sym

Min

Typ1

Max

Unit

Test Conditions

1. Typical values are at 25C and 3.3V. They are for design aid only; not guaranteed and not subject to production testing.

2. Not production tested, guaranteed by design and other correlation factors.

RSOCLKN

RSOCLKP

RPOS

RNEG

RSOCLKPD

RPOCLK*

RPOD<0:7>

ROFP

RPOCLKPD

ROFPPD

*This shows timing in HW mode. In SW mode (HWSEL=1) this clock polarity can be inverted. See Table 8 for details.

Table 31. Receive Analog Characteristics

Parameter

Note

Min

Typ1

Max

Unit

Test Conditions

End to end loss budget (coax)1

BER=1E-12. PRBS (23) data.

CMI encoded. Input white noise

=5mV RMS max.

LOS - fiber

Assert

µsec

Nodatatransition. Default LOS

setting.

De-assert

187.5

µsec

No LOS events. Default LOS

settings.

1. Typical values are at 25C and 3.3V. They are for design aid only; not guaranteed and not subject to production testing.

2. Not production tested, guaranteed by design and other correlation factors.

LXT6155LE Datasheet(PDF) 40 Page - Intel Corporation

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