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RT1716WSC Datasheet(PDF) 18 Page - Richtek Technology Corporation |
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RT1716WSC Datasheet(HTML) 18 Page - Richtek Technology Corporation |
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18 / 37 page ![]() RT1716 18 DS1716-04 March 2020 www.richtek.com © Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Address Length Register Name Bit BitName Default Type Description 0x19 1 TCPC_C ONTROL 7:5 Reserved 000 R Reserved 4 Reserved 0 R Reserved 3:2 I2C_CK_ STRETCH 00 R Not support. 1 BIST_TEST_ MODE 0 RW 0b : Normal Operation. Incoming messages enabled by RECEIVE_DETECT passed to TCPM via Alert. (default) 1b : BIST Test Mode. Incoming messages enabled by RECEIVE_DETECT result in GoodCRC response but may not be passed to the TCPM via Alert. TCPC may temporarily store incoming messages in the Receive Message Buffer, but this may or may not result in a Receive SOP* Message Status or a Rx Buffer Overflow alert. 0 PLUG_ORIENT 0 RW 0b : When VCONN is enabled, apply it to the CC2 pin. Monitor the CC1 pin for BMC communications if PD messaging is enabled. (default) 1b : When VCONN is enabled, apply it to the CC1 pin. Monitor the CC2 pin for BMC communications if PD messaging is enabled. Required 0x1A 1 ROLE_C ONTROL 7 Reserved 0 R Reserved 6 DRP 0 RW 0b : No DRP. Bits B3..0 determine Rp/Rd/Ra settings (default) 1b: DRP 5:4 RP_VALUE 00 RW 00b : Rp default (default) 01b : Rp 1.5A 10b : Rp 3.0A 11b : Reserved 3:2 CC2 10 RW 00b : Reserved 01b : Rp (Use Rp definition in B5..4) 10b : Rd (default) 11b : Open (Disconnect or don’t care) Set to 11b if enabling DRP in B7..6 1:0 CC1 10 RW 00b : Reserved 01b : Rp (Use Rp definition in B5..4) 10b : Rd (default) 11b : Open (Disconnect or don’t care) Set to 11b if enabling DRP in B7..6 |
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