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ES9826 Datasheet(PDF) 43 Page - ESS Technology,Inc

Part # ES9826
Description  32-bit High performance 2 Channel ADC w/PGA
PDF  88 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9826 Datasheet(HTML) 43 Page - ESS Technology,Inc

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ES9826 Datasheet
VERSION 0.1.2
43
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM
Audio Interface Timing
Audio data on DATA1-2 are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time
requirements relative to the rising edge of DATA_CLK.
Figure 18 – Audio interface timing
Parameter
Symbol
Min
Max
Unit
DATA_CLK pulse width high
tDCH
9.0
ns
DATA_CLK pulse width low
tDCL
9.0
ns
DATA_CLK cycle time
tDCY
20
ns
DATA_CLK duty cycle
45:55
55:45
DATAx set-up time to DATA_CLK rising edge
tDS
4.1
ns
DATAx hold time to DATA_CLK rising edge
tDH
2.0
ns
Table 9 - Audio interface timing definitions



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