ES9826 datasheet(49/88 Pages) ESS

49 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Default

1'b0

1'b1

1'b0

1'b1

Bits

Mnemonic

Description

[7]

FORCE_PHASE_ADC_CLK

Forces the ADC_CLK phase to use the state of Reg4[6]

ADC_CLK_INV.

• 1'b0: Automatically determine the best phase. (default)

• 1'b1: Use the state of ADC_CLK_INV

[6]

RESERVED

[5]

FORCE_PHASE_CLK_IADC

Sets phase of CLK_IADC with the value of PHASE_CLK_IADC.

• 1'b0: Auto phase tuning if

AUTO_CLK_IADC_PHASE_SYNC is set

• 1'b1: Sets phase by PHASE_CLK_IADC

[4]

PHASE_CLK_IADC

Sets phase of CLK_IADC relative to MCLK when

FORCE_PHASE_CLK_IADC is set. Only used when MCLK is

faster than CLK_IADC.

• 1'b0: Phase 0 (default)

• 1'b1: Phase 1

[3]

AUTO_CLK_IADC_PHASE_SYNC

Allows phase of CLK_IADC to be tuned automatically according

to ADC input data. Only used when MCLK is faster than

CLK_IADC.

• 1'b0: CLK_IADC phase tuning disabled

• 1'b1: Auto CLK_IADC phase tuning (default)

[2]

AUTO_WS_PHASE_SYNC

Uses WS input from GPIO2 as the sync reference.

• 1'b0: WS is not the sync reference

• 1'b1: WS is the sync reference

[1]

AUTO_ICG_SYNC

Allows programmable clock dividers to auto sync to the

reference.

• 1'b0: Auto sync disabled

• 1'b1: Auto sync enabled (default)

[0]

AUTO_FS_CLK_GEN_SYNC

Allows FS signals to auto sync to the reference.

• 1'b0: Auto sync disabled

• 1'b1: Auto sync enabled (default)

ES9826 Datasheet(PDF) 49 Page - ESS Technology,Inc

ES9826 Datasheet(HTML) 49 Page - ESS Technology,Inc

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