ES9826 datasheet(76/88 Pages) ESS

76 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

Bits

[7]

[6]

[5:0]

Default

Bits

Mnemonic

Description

[7]

RATIO_VALID

Validity of the MCLK/CLK_ADC ratio.

(

N + 1

) ∗ 128 MCLK periods in a WS frame.

• 1'b0: Invalid ratio

• 1'b1: Valid ratio

[6]

ADC_HALF_DIV_AUTO

Result (M) of the automatic sample rate detect (reg0[5]

AUTO_FS_DETECT) logic.

• 1'b0: CLK_ADC is an integer multiple of MCLK, M = 1.

• 1'b1: CLK_ADC is a N*0.5 multiple of MCLK, M = 2.

[5:0]

ADC_DIV_AUTO

Result (N) of the automatic sample rate detect (reg0[5]

AUTO_FS_DETECT) logic.

�� [��] =

�� ∗ ��

(�� + 1) ∗ 128

Bits

[7]

[6]

[5]

[4:0]

Default

Bits

Mnemonic

Description

[7]

CH2_DC_VALID

Validity of the CH2 DC value.

• 1'b0: Invalid

• 1'b1: Valid

[6]

CH1_DC_VALID

Validity of the CH1 DC value.

• 1'b0: Invalid

• 1'b1: Valid

[5]

TDM_VALID

TDM valid flag

• 1'b0: Invalid

• 1'b1: Valid

[4:0]

AUTO_CH_NUM

Result of the automatic TDM channel logic.

Note: Requires reg6[7] AUTO_CH_DETECT to enable

functionality.

ES9826 Datasheet(PDF) 76 Page - ESS Technology,Inc

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