ES9826 datasheet(50/88 Pages) ESS

50 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

Bits

[7:0]

Default

8'd7

Bits

Mnemonic

Description

[7:0]

MASTER_BCK_DIV

Master decoding clock divider.

Whole number divide value + 1 for CLK_BCK_WS_GEN

(MCLK/divide_value).

Bits

[7]

[6]

[5:4]

[3]

[2]

[1]

[0]

Default

1'b0

2'b00

1'b0

1'b1

1'b0

Bits

Mnemonic

Description

[7]

ADC_CLK_DIV2

Sets ADC clock rate.

• 1'b0: Full rate (default)

• 1'b1: 1/2 rate

[6]

ADC_CLK_INV

Inverts the phase of ADC_CLK.

• 1'b0: Non-inverted (default)

• 1'b1: Inverted

Note: Requires Reg2[7] FORCE_PHASE_ADC_CLK = 1'b1.

[5:4]

MASTER_FRAME_LENGTH

Selects the bit length of the I2S/TDM channels in master mode.

• 2'b00: 32-bit (default)

• 2'b10: 16-bit

• Others: Reserved

[3]

MASTER_WS_PULSE_MODE

When enabled, master WS is a 1 BCK pulse signal instead of a

50% duty cycle signal.

• 1'b0: 50% duty cycle WS signal (default)

• 1'b1: Pulse WS signal

[2]

MASTER_BCK_INVERT

Inverts master BCK.

• 1'b0: Non-inverted

• 1'b1: Inverted (default)

[1]

MASTER_WS_INVERT

Inverts master WS.

• 1'b0: Non-inverted (default)

• 1'b1: Inverted

[0]

MASTER_MODE_ENABLE

Enables I2S/TDM master mode and generates master BCK and

master WS.

• 1'b0: Disabled

• 1'b1: Enabled (default)

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