 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ES9826 Datasheet(PDF) 54 Page - ESS Technology,Inc |
|
|
|||||||||||||||||||||||||||||
ES9826 Datasheet(HTML) 54 Page - ESS Technology,Inc |
|
|
54 / 88 page  ES9826 Datasheet VERSION 0.1.2 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM 54 Register 19: INTERRUPT CLEAR Bits [7:2] [1] [0] Default 1'b0 1'b0 1'b0 Bits Mnemonic Description [7:2] RESERVED NA [1] INT_CLEAR_CH2_PEAK_LATCH Clears the latched PEAK_FLAG interrupt on ADC CH2. • 1'b0: Interrupt held if asserted (default) • 1'b1: Interrupt cleared [0] INT_CLEAR_CH1_PEAK_LATCH Clears the latched PEAK_FLAG interrupt on ADC CH1. • 1'b0: Interrupt held if asserted (default) • 1'b1: Interrupt cleared Register 24-20: RESERVED Register 25: VREF CONFIG Bits [7:1] [0] Default 7'b0000000 1'b0 Bits Mnemonic Description [7:1] RESERVED NA [0] ENFCB Enable the fast charge of the ADC reference voltage. • 1'b0: Fast charge enabled (default) • 1'b1: Fast charge disabled |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
