ES9826 datasheet(72/88 Pages) ESS

72 / 88 page

ES9826 Datasheet

VERSION 0.1.2

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM

PLL Registers

Bits

[7]

[6]

[5:1]

[0]

Default

1'b0

5'd0

1'b0

Bits

Mnemonic

Description

[7]

AO_SOFT_RESET

Performs soft reset to digital core and clocked registers (0-80).

[6]

PLL_SOFT_RESET

Performs soft reset to only the PLL registers (192-206).

[5:1]

RESERVED

[0]

PLL_CLK_PHASE_INV

Inverts the PLL clock output.

• 1'b0: Non-inverted (default)

• 1'b1: Inverted

Bits

[7:6]

[5:4]

[3]

[2:1]

[0]

Default

2'b01

2'b10

1'b0

2'b00

1'b1

Bits

Mnemonic

Description

[7:6]

RESERVED

[5:4]

SEL_PLL_CLK_IN

Selects PLL input clock source when EN_PLL_CLK_IN is set.

• 2'b00: ACLK

• 2'b10: BCK (default)

• Others: Reserved

[3]

EN_PLL_CLK_IN

Allows SEL_PLL_CLK_IN to select PLL input clock source.

• 1'b0: Disabled (default)

• 1'b1: Enabled

[2:1]

SEL_MCLK_IN

Selects digital core and ADC clock source when EN_MCLK_IN

is set.

• 2'b00: ACLK

• 2'b10: PLL_CLK

• Others: Reserved

[0]

EN_MCLK_IN

Enables clock inputs to the digital core.

• 1'b0: Disabled

• 1'b1: Enabled (default)

ES9826 Datasheet(PDF) 72 Page - ESS Technology,Inc

ES9826 Datasheet(HTML) 72 Page - ESS Technology,Inc

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