TPS274C65AS datasheet(32/87 Pages) TI

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The device is disabled and the digital registers

are reset.

VDD rises.

Normal powerup operation

VDD

VDD decreases below VUVLOF.

VOUTx

VHYS

VVDD_UVLOR

tDLY_RST

VVDD_UVLOF

Figure 9-25. VDD UVLO

9.3.5.7 Power-Up and Power-Down Behavior

Device is in OFF or POR state when the device is not powered. FAULT, READY and VOUTx will be in high-Z

state.

Once the VS > VS_UVPR and VDD > VDD,UVLOR, the device starts to read in the configurations and READY will be

pulled low when the device is ready for the SPI communication.

In case the VDD power supply is enabled the first and the VDD voltage exceeds VDD,UVLOR before the VS supply

is up and VS voltage exceeds VS_UVPR, the outputs remain disabled.

9.3.5.8 Reverse Current Blocking

Reverse current occurs when VVS<VOUT. In this case, current will flow from VOUTx to VS. Reverse current can be

caused by miswiring at the output, or a capacitive or inductive load can cause inverse current. For example, if

there is a significant amount of load capacitance and the VS node has a transient droop, VOUTx may be greater

than VS. The VSdroop may be caused by inrush current from a different load. Similarly load/supply faults and

inductive loads can cause supply to be pushed up as well. Another application is to provide protection when

output connection to supply (miswiring) occurs when the input power supply is not available or connected. The

device monitors VS and VOUT to provide true reverse current blocking when a reverse condition or input power

failure condition is detected.

TPS274C65

SLVSFZ2B – APRIL 2023 – REVISED OCTOBER 2023

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TPS274C65AS Datasheet(PDF) 32 Page - Texas Instruments