| Electronic Components Datasheet Search |
|
TPS274C65AS Datasheet(PDF) 9 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TPS274C65AS Datasheet(HTML) 9 Page - Texas Instruments |
|
9 / 87 page ![]() 7.5 Electrical Characteristics (continued) VVS = 11 V to 36 V, VVDD = 3.0 V to 5.5 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOUT,LEAKX Leakage current from OUT to GND in OFF state Vs = VOUT < 36 V, Switch and all diagnostics disabled, measured into the OUTx pin 40 µA IOUT(OFF) Output leakage current (per channel) VS <= 36 V, VOUT = 0 Channel disabled, diagnostics disabled Tj <= 125°C 0 0.8 10 µA VDD IQ VDD quiescent current, SCLK ON, all diagnostics disabled, (WB_OFF, WB_ON, SHRT_VS, ADC) external VDD VS ≤ 36 V, VDD = 5.5 V All channels enabled, IOUTx = 0 A 1.3 1.6 mA VDD IQ VDD quiescent current, SCLK ON, all diagnostics disabled, (WB_OFF, WB_ON, SHRT_VS, ADC) external VDD VS ≤ 36 V, VDD = 3.0 V All channels enabled, IOUTx = 0 A 1 1.2 mA VDD IQ VDD quiescent current, SCLK off, all diagnostics disabled ((WB_OFF, WB_ON, SHRT_VS), ADC enabled and converting, external VDD VS ≤ 36 V, VDD = 5.5 V All channels enabled, IOUTx = 0 A 1.2 1.6 mA VS IQ VS quiescent current, SCLK off, all diagnostics disabled, (WB_OFF, WB_ON, SHRT_VS, ADC) internal VDD VS ≤ 36 V, All channels enabled, IOUTx = 0 A 2.8 3.2 mA VS IQ VS quiescent current, SCLK off, all diagnostics (WB_OFF, WB_ON, SHRT_VS, ADC) enabled, external VDD VS ≤ 36 V, VDD = 3.0 V All channels enabled, IOUTx = 0 A 1.7 2.5 mA VS IQ VS quiescent current, SCLK off, all diagnostics (WB_OFF, WB_ON, SHRT_VS, ADC) disabled, RCB enabled, external VDD VS ≤ 36 V, VDD = 3.0 V All channels enabled, IOUTx = 0 A 1.4 2.45 mA Ileak_LG Leakage current out of the output pins with the GND of IC disconnected, Load ground connected to supply ground VS≤ 30 V, VDD = 5.5 V, RL = 24 Ω All channels enabled 0.8 0.9 mA RON CHARACTERISTICS RON On-resistance (Includes MOSFET and package) 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 = 200 mA TJ = 25°C 72 mΩ TJ = 125°C 110 mΩ On-resistance when 2 channels are paralleled (Includes MOSFET and package) 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 > 200 mA. VOUT1 tied to VOUT2 TJ = 25°C 33 mΩ TJ = 125°C 55 mΩ VDD_REG CHARACTERISTICS VVDD VDD Output voltage (Internal regulator enabled) 6 V ≤ VS ≤ 36 V, IVDD < 20 mA Includes load and line regulation across the range. 3.1 3.3 3.6 V www.ti.com TPS274C65 SLVSFZ2B – APRIL 2023 – REVISED OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS274C65 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |