TPS274C65AS datasheet(18/87 Pages) TI

18 / 87 page

different modes of SPI that is fixed for a given system implementation and cannot be changed dynamically or on

the fly. The two modes can be used with or without CRC.

The two modes are described in detail:

1. Addressable SPI mode - non-daisy-chained SPI bus with one single/shared CS through chip addressing.

Each chip on the shared SPI is assigned an individual chip address with the address set through a resistor

(three-bit address for the chip). Addressed SPI (DSPI pin pulled low) allows direct communication with up

to eight TPS274C65xS on a shared SPI using a single shared CS signal. The three-bit address of each IC

(up to eight on one board) is set with a resistor to GND on this pin Addressed SPI offers the advantage

of direct chip access. CRC check is enabled when CRCEN=1. The SPI main device addresses a specific

chip by sending the appropriate A2, A1, A0 logic in the first three bits of the SPI read/write command. The

TPS274C65xS monitors the SPI address in each SPI read or write cycle and responds appropriately when

the address matches the programmed address for that IC. The added advantage is that it is possible to

update the SW state register and read the data in the various read only fault and data registers in every read

as well as write command frame. The transmission speed will be faster for addressable SPI compared to the

daisy chain SPI as the direct data transmission will happen immediately once the address is transmitted.

2. Daisy chain SPI mode is enabled by setting DSPI pin high. In this mode, multiple TPS274C65xS devices

are configured in a serial fashion. In the 16-bit daisy-chain mode, only a minimum read capability and Switch

state ON/OFF write is possible- the FAULT status can be read out on each write to the switch ON-OFF

update the switch state. However, it is possible to update the SW state register and read the data in the

various read only fault and data registers. The 24-bit SPI format allows the write to the SW_STATE register

in every read as well as write command frame as well enable CRC. The speed of the transmission for daisy

chain will be depending on the CLK frequency as well as the number of devices connected in series.

The communication between the TPS274C65 IC and the controller or MCU is through a SPI bus in a master-

slave configuration. The external MCU is always an SPI master that sends command requests on the SDI pin of

the TPS274C65 IC and receives device responses on the SDO pin of the IC. The TPS274C65 device is always

an SPI slave device that receives command requests and sends responses (such as status and measured

values) to the external MCU over the SDO line. The following lists the characteristics of the SPI:

The TPS274C65 device can be connected to the master MCU in the following formats.

• One slave device

TPS274C65

SLVSFZ2B – APRIL 2023 – REVISED OCTOBER 2023

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TPS274C65AS Datasheet(PDF) 18 Page - Texas Instruments