 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TPS274C65AS Datasheet(PDF) 53 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TPS274C65AS Datasheet(HTML) 53 Page - Texas Instruments |
|
|
53 / 87 page  Table 9-17. WB_OFF_CH_STAT Register Field Descriptions (continued) Bit Field Type Reset Description 0 WB_OFF_CH1 RC 0h The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH1. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (off-state) fault in CH1 1h = Wire break (open load) fault in off-state has occurred in CH1 9.6.6 WB_ON_CH_STAT Register (Offset = 5h) [Reset = 00h] WB_ON_CH_STAT is shown in Table 9-18. Return to the Summary Table. The register reports faulted channel(s) with the on-state wire-break fault Table 9-18. WB_ON_CH_STAT Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h Reserved 3 WB_ON_CH4 RC 0h The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH4. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (on-state) fault in CH4 1h = Wire break (open load) fault in on-state has occurred in CH4 2 WB_ON_CH3 RC 0h The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH3. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (on-state) fault in CH3 1h = Wire break (open load) fault in on-state has occurred in CH3 1 WB_ON_CH2 RC 0h The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH2. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition is cleared. 0h = No wire-break (on-state) fault in CH2 1h = Wire break (open load) fault in on-state has occurred in CH2 0 WB_ON_CH1 RC 0h The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH1. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (on-state) fault in CH1 1h = Wire break (open load) fault in on-state has occurred in CH1 9.6.7 ILIMIT_CH_STAT Register (Offset = 6h) [Reset = 00h] ILIMIT_CH_STAT is shown in Table 9-19. Return to the Summary Table. The register reports faulted channel(s) with the current limit fault Table 9-19. ILIMIT_CH_STAT Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h Reserved www.ti.com TPS274C65 SLVSFZ2B – APRIL 2023 – REVISED OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TPS274C65 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
