AD9949 datasheet(5/36 Pages) AD

5 / 36 page

AD9949

Rev. B | Page 5 of 36

TIMING SPECIFICATIONS

CL = 20 pF, fCLI = 36 MHz, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK (CLI) (See Figure 16)

CLI Clock Period

tCLI

27.8

CLI High/Low Pulse Width

tADC

11.2

13.9

16.6

Delay from CLI to Internal Pixel Period Position

tCLIDLY

CLPOB PULSE WIDTH (PROGRAMMABLE)1

tCOB

Pixels

SAMPLE CLOCKS (See Figure 18)

SHP Rising Edge to SHD Rising Edge

tS1

12.5

13.9

DATA OUTPUTS (See Figure 19 and Figure 20)

Output Delay From Programmed Edge

tOD

Pipeline Delay

Cycles

SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15)

Maximum SCK Frequency

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

SCK Falling Edge to SDATA Valid Read

tDV

1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.

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