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AD9949

Rev. B | Page 25 of 36

POWER-UP PROCEDURE

RECOMMENDED POWER-UP SEQUENCE

When the AD9949 is powered up, the following sequence is

recommended (refer to Figure 27 for each step):

Turn on the power supplies for the AD9949.

Apply the master clock input, CLI, VD, and HD.

Although the AD9949 contains an on-chip, power-on reset,

a software reset of the internal registers is recommended.

Write a 1 to the SW_RST register (Address 0×10), which

resets the internal registers to their default values. This bit

is self-clearing and automatically resets back to 0.

The Precision Timing core must be reset by writing a 0 to

the TGCORE_RSTB register (Address 0×12) followed by

writing a l to the TGCORE_RSTB register. This starts the

internal timing core operation.

Write a 1 to the PREVENTUPDATE register (Address

0×14). This prevents the updating of the serial register

data.

Write to the desired registers to configure high speed

timing and horizontal timing.

Write a 1 to the OUT_CONTROL register (Address 0×11).

This allows the outputs to become active after the next

VD/HD rising edge.

Write a 0 to the PREVENTUPDATE register (Address

0×14). This allows the serial information to be updated at

next VD/HD falling edge.

The next VD/HD falling edge allows register updates to

occur, including OUT_CONTROL, which enables all clock

outputs.

VDD

(INPUT)

SERIAL

WRITES

(OUTPUT)

ODD FIELD

EVEN FIELD

...

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS

UPDATED AT VD/HD EDGE

H1/H3, RG

H2/H4

tPWR

CLI

(INPUT)

(OUTPUT)

...

Figure 27. Recommended Power-Up Sequence

AD9949 Datasheet(PDF) 25 Page - Analog Devices

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