AD9949 datasheet(30/36 Pages) AD

30 / 36 page

AD9949

Rev. B | Page 30 of 36

APPLICATIONS INFORMATION

CIRCUIT CONFIGURATION

The AD9949 recommended circuit configuration is shown in

Figure 38. Achieving good image quality from the AD9949

requires careful attention to PCB layout. All signals should be

routed to maintain low noise performance. The CCD output

signal should be directly routed to Pin 27 through a 0.1 µF

capacitor. The master clock CLI should be carefully routed to

Pin 25 to minimize interference with the CCDIN, REFT, and

REFB signals.

The digital outputs and clock inputs are located on Pins 1 to 13

and Pins 31 to 40 and should be connected to the digital ASIC

away from the analog and CCD clock signals. Placing series

resistors close to the digital output pins may help to reduce

digital code transition noise. If the digital outputs must drive a

load larger than 20 pF, buffering is recommended to minimize

additional noise. If the digital ASIC can accept gray code, the

AD9949’s outputs can be selected to output data in gray code

format using the control register Bit D5. Gray coding helps reduce

potential digital transition noise compared with binary coding.

The H1–H4 and RG traces should have low inductance to avoid

excessive distortion of the signals. Heavier traces are recom-

mended because of the large transient current demand on

H1–H4 from the capacitive load of the CCD. If possible,

physically locating the AD9949 closer to the CCD will reduce

the inductance on these lines. As always, the routing path

should be as direct as possible from the AD9949 to the CCD.

GROUNDING AND DECOUPLING

RECOMMENDATIONS

As shown in Figure 38, a single ground plane is recommended

for the AD9949. This ground plane should be as continuous as

possible, particularly around Pins 23 to 30. This ensures that all

analog decoupling capacitors provide the lowest possible

impedance path between the power and bypass pins and their

respective ground pins. All high frequency decoupling

capacitors should be located as close as possible to the package

pins. It is recommended that the exposed paddle on the bottom

of the package be soldered to a large pad, with multiple vias

connecting the pad to the ground plane.

All the supply pins must be decoupled to ground with good

quality, high frequency chip capacitors. There should also be a

4.7 µF or larger bypass capacitor for each main supply—AVDD,

RGVDD, HVDD, and DRVDD—although this is not necessary

for each individual pin. In most applications, it is easier to share

the supply for RGVDD and HVDD, which may be done as long

as the individual supply pins are separately bypassed. A separate

3 V supply may be used for DRVDD, but this supply pin should

still be decoupled to the same ground plane as the rest of the

chip. A separate ground for DRVSS is not recommended.

The reference bypass pins (REFT, REFB) should be decoupled

to ground as close as possible to their respective pins. The

analog input (CCDIN) capacitor should also be located close to

the pin.

3V ANALOG SUPPLY

SERIAL

INTERFACE

CCD SIGNAL

VD/HD/HBLK INPUTS

CLP/BLK OUTPUT

DRIVER

SUPPLY

RG DRIVER

SUPPLY

H DRIVER

SUPPLY

MASTER

CLOCK INPUT

3V ANALOG

SUPPLY

DATA

OUTPUTS

H1 TO H4

TOP VIEW

AD9949

PIN 1

IDENTIFIER

REFB

REFT

AVSS

CCDIN

AVDD

CLI

TCVDD

TCVSS

RGVDD

D1 1

D2 2

D3 3

D4 4

DRVDD 6

D5 7

D6 8

D7 9

D8 10

RG OUTPUT

DRVSS 5

4.7

µF 0.1µF

0.1

µF

4.7

µF

4.7

µF

0.1

µF

0.1

µF

4.7

µF

0.1

µF

0.1

µF

0.1

µF

Figure 38. Recommended Circuit Configuration

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