AD9949 datasheet(14/36 Pages) AD

14 / 36 page

AD9949

Rev. B | Page 14 of 36

Table 8. AFE Register Map

Address

Data Bit

Content

Default Value

Name

Description

[11:0]

OPRMODE

AFE Operation Modes. (See Table 14.)

[9:0]

VGAGAIN

VGA Gain.

[7:0]

CLAMP LEVEL

Optical Black Clamp Level.

[11:0]

CTLMODE

AFE Control Modes. (See Table 15.)

[17:0]

PxGA GAIN01

PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].

[17:0]

PxGA GAIN23

PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].

Table 9. Miscellaneous Register Map

Address

Data Bit

Content

Default Value

Name

Description

[0]

SW_RST

Software Reset.

1 = Reset all registers to default, then self-clear back to 0.

[0]

OUT_CONTROL

Output Control.

0 = Make all dc outputs inactive.

[0]

TGCORE_RSTB

Timing Core Reset Bar.

0 = Reset TG core.

1 = Resume operation.

[11:0]

UPDATE

Serial Update.

Sets the line (HD) within the field to update serial data.

[0]

PREVENTUPDATE

Prevents the update of the VD updated registers.

1 = Prevent Update.

[0]

VDHDEDGE

VD/HD Active Edge.

0 = Falling Edge Triggered.

1 = Rising Edge Triggered.

[1:0]

FIELDVAL

Field Value Sync.

0 = Next Field 0.

1 = Next Field 1.

2/3 = Next Field 2.

[0]

HBLKRETIME

Retime HBLK to Internal H1 Clock.

Preferred setting is 1. Setting to 1 adds one cycle delay to HBLK

toggle positions.

[1:0]

CLPBLKOUT

CLP/BLK Pin Output Select.

0 = CLPOB.

1 = PBLK.

2 = HBLK.

3 = Low.

[0]

CLPBLKEN

Enable CLP/BLK Output.

1 = Enable.

[0]

TEST MODE

Internal Test Mode.

Should always be set high.

AD9949 Datasheet(PDF) 14 Page - Analog Devices

AD9949 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL