AD9949 datasheet(29/36 Pages) AD

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AD9949

Rev. B | Page 29 of 36

The PxGA gain for each of the four channels is variable from

0 dB to 18 dB in 512 steps, specified using the PxGA GAIN01

and PxGA GAIN23 registers. The PxGA gain curve is shown in

Figure 36. The PxGA GAIN01 register contains nine bits each

for PxGA Gain0 and Gain1, and the PxGA GAIN23 register

contains nine bits each for PxGA Gain2 and Gain3.

PxGA GAIN REGISTER CODE

128

192

256

320

384

448

511

Figure 36. PxGA Gain Curve

VARIABLE GAIN AMPLIFIER

The VGA stage provides a gain range of 6 dB to 42 dB, pro-

grammable with 10-bit resolution through the serial digital

interface. The minimum gain of 6 dB is needed to match a 1 V

input signal with the ADC full-scale range of 2 V. When com-

pared to 1 V full-scale systems, the equivalent gain range is 0

dB to 36 dB.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain can be calculated for any gain register value by

using the equation

Gain (db) = (0.0351 × Code) + 6 dB

where the code range is 0 to 1023.

There is a restriction on the maximum amount of gain that can

be applied to the signal. The PxGA can add as much as 18 dB,

and the VGA is capable of providing up to 42 dB. However, the

maximum total gain from the PxGA and VGA is restricted to

42 dB. If the registers are programmed to specify a total gain

higher than 42 dB, the total gain is clipped at 42 dB.

ADC

The AD9949 uses a high performance ADC architecture,

optimized for high speed and low power. DNL performance is

typically better than 0.5 LSB. The ADC uses a 2 V input range.

See Figure 9 and Figure 10 for typical linearity and noise

performance plots for the AD9949.

VGA GAIN REGISTER CODE

1023

127

255

383

511

639

767

895

Figure 37. VGA Gain Curve (PxGA Not Included)

OPTICAL BLACK CLAMP

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel in-

terval on each line, the ADC output is compared with a fixed

black level reference, selected by the user in the clamp level regis-

ter. The value can be programmed between 0 LSB and 255 LSB

in 256 steps. The resulting error signal is filtered to reduce noise,

and the correction value is applied to the ADC input through a

DAC. Normally, the optical black clamp loop is turned on once

per horizontal line, but this loop can be updated more slowly to

suit a particular application. If external digital clamping is used

during the postprocessing, the AD9949 optical black clamping

may be disabled using Bit D2 in the OPRMODE register. When

the loop is disabled, the clamp level register may still be used to

provide programmable offset adjustment.

The CLPOB pulse should be placed during the CCD’s optical

black pixels. It is recommended that the CLPOB pulse duration

be at least 20 pixels wide to minimize clamp noise. Shorter pulse

widths may be used, but clamp noise may increase and the

ability to track low frequency variations in the black level will

be reduced. See the Horizontal Clamping and Blanking and

Applications Information sections for timing examples.

DIGITAL DATA OUTPUTS

The AD9949 digital output data is latched using the DOUT

phase register value, as shown in Figure 28. Output data timing

is shown in Figure 19 and Figure 20. It is also possible to leave

the output latches transparent, so that the data outputs are valid

immediately from the ADC. Programming the AFE control

data outputs can also be disabled (three-stated) by setting the

AFE control register Bit D3 to a 1.

The data output coding is normally straight binary, but the

coding may be changed to gray coding by setting the AFE

control register Bit D5 to a 1.

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