RF Micro Devices Inc.

7628 Thorndike Road, Greensboro, NC 27409-9421

DS20151001

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The information in this publication is believed to be accurate. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents or other rights of

third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended

application circuitry and specifications at any time without prior notice.

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RF5216

MIPI

Location

Bit Name

Default

Description

R/W

Broadcast

ID support

Trigger

support

Reg1A[3]

DATA_FRAME_PARITY_ERR

0

Data Frame received with a parity error

R/W

N

N

Reg1A[2]

READ_UNUSED_REG

0

Read Command Sequence received with an

invalid address

R/W

N

N

Reg1A[1]

WRITE_UNUSED_REG

0

Write Command Sequence received with an

invalid address

R/W

N

N

Reg1A[0]

BID_GID_ERR

0

Read Command Sequence received with a

BROADCAST_ID or GROUP_SID.

R/W

N

N

Register 1Bh (11011b) – Group Slave ID

MIPI

Location

Bit Name

Default

Description

R/W

Broadcast

ID support

Trigger

support

Reg1B[7:4]

RESERVED

0000

Reserved

R

N

N

Reg1B[3:0]

GSID[3:0]

0000

Group Slave ID

R/W

N

N

Register 1Ch (11100b) – Power Mode Trigger

MIPI

Location

Bit Name

Default

Description

R/W

Broadcast

ID support

Trigger

support

Reg1C[7:6]

PWR_MODE[7:6]

00

00: ACTIVE – Normal Operation

01: STARTUP – Reset all registers to default settings

10: LOW POWER – Retain register values, Band-Gap

off

11: Reserved

Note: Setting PWR_MODE to STARTUP is identical to

a hardware reset initiated by the VIO signal.

R/W

Y

N

Reg1C[5]

Trigger_Mask_2

0

If this bit is set, trigger 2 is disabled. When all triggers

are disabled, if writing to a register that is associated

with trigger 2, the data goes directly to the destination

register.

R/W

N

N

Reg1C[4]

Trigger_Mask_1

0

If this bit is set, trigger 1 is disabled. When all triggers

are disabled, if writing to a register that is associated

with trigger 1, the data goes directly to the destination

register.

R/W

N

N

Reg1C[3]

Trigger_Mask_0

0

If this bit is set, trigger 0 is disabled. When all triggers

are disabled, if writing to a register that is associated

with trigger 0, the data goes directly to the destination

register.

R/W

N

N

Reg1C[2]

Trigger_2

0

A write of a 1 to this bit loads trigger 2’s registers.

R/W

Y

N

Reg1C[1]

Trigger_1

0

A write of a 1 to this bit loads trigger 1’s registers.

R/W

Y

N

Reg1C[0]

Trigger_0

0

A write of a 1 to this bit loads trigger 0’s registers.

R/W

Y

N