Analog Integrated Circuit Device Data

12

Freescale Semiconductor

33970

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

SPI PROTOCOL DESCRIPTION

The SPI interface has a full-duplex, three-wire

synchronous, 16-bit serial synchronous interface data

Serial Clock (SCLK), Serial Input (SI), and Serial Output

(SO). The SI/SO pins of the 33970 follow a first in/first out

(D15/D0) protocol with both input and output words

transferring the most significant bit first. All inputs are

compatible with 5.0 V CMOS logic levels.

LOGIC COMMANDS AND REGISTERS

This section provides a description of the 33970 SPI behavior. To follow the explanations below, refer to Table 5 and to the

timing diagrams shown in Figure 6 and Figure 7.

Figure 6. Single 16-Bit Word SPI Communication

Figure 7. Multiple 16-Bit Word SPI Communication

Table 5. Data Transfer Timing

Pin

Description

CS

(1-to-0)

SO pin is enabled.

CS

(0-to-1)

33970 configuration and desired output states are transferred and executed according to the data in

the Shift registers.

SO

Will change state on the rising edge of the SCLK pin signal.

SI

Will accept data on the falling edge of the SCLK pin signal.

CS

SCLK

SI

SO

Output shift register is loaded here.

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

OD15

OD14

OD13

OD12

OD11

OD10

OD9

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

Note SO is tri-stated when CS is logic [1].

CS

SCLK

SI

SO

D15

D14

D13

D12

D11

D2

D1

D0

D15

*

D14

*

D13

*

D4

D3

D2

*

D1

*

D0

*

OD15

OD14

OD13

OD12

OD11

OD2

OD1

OD0

D15

D14

D13

OD4

OD3

D2

D1

D0

Notes

2. D15, D14, D13, ..., and D0 refer to the first 16 bits of data into the 33970.

3. D15

4. OD15, OD14, OD13, ..., and OD0 refer to the first 16 bits of fault and status data out of the 33970.

1. SO is tri-stated when CS is logic [1].