33970 datasheet(16/36 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33970

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

The bits in Table 9 are write-only.

P012 (D12)—This bit must be transmitted as logic [0] for

valid commands.

P011:P00 (D11:D0)—Desired pointer position of

Gauge 0. Pointer positions can range from 0

(000000000000) to position 4095 (111111111111). For a

step motor requiring 12 microsteps per degree of pointer

movement, the maximum pointer sweep is 341.25

°.

The bits in Table 10 are write-only.

P1 12 (D12)—This bit must be transmitted as logic [0] for

valid commands.

P1 11:P1 0 (D11:D0)—Desired pointer position of

Gauge 1. Pointer positions can range from 0

(000000000000) to position 4095 (111111111111). For a

step motor requiring 12 microsteps per degree of pointer

movement, the maximum pointer sweep is 341.25

(4095

÷ 12).

Address 100—Gauge Return to Zero Register (RTZR)

Gauge Return to Zero Register (RTZR) (refer to Table 11)

is written to return the gauge pointers to the zero position.

During an RTZ event, the pointer is returned to zero using full

steps, where only one coil is driven at any point in time. The

back electromotive force (EMF) signal present on the non-

driven coil is integrated and its results are stored in an

accumulator.

A logic [1] written to bit RZ1 enables a Return to Zero for

Gauge 0 if RZ0 is logic [0], and Gauge 1 if RZ0 is logic [1],

respectively. Similarly, a logic [0] written to bit RZ1 disables a

Return to Zero for Gauge 0 when RZ0 is logic [0], and

Gauge 1 when RZ0 is logic [1], respectively.

Bits D12:D5 and D3:D2 must be at logic [0] for valid RTZR

commands.

Bit RZ4 is used to enable an unconditional RTZ event. A

logic [0] results in a typical RTZ event, automatically

providing a Stop when a stall condition is detected. A logic [1]

will result in RTZ movement, causing a Stop if a logic [0] is

written to bit RZ0. This feature is useful during development

and characterization of RTZ requirements.

The register bits in Table 11 are write-only.

RZ12:RZ5 (D12:D5)—These bits must be transmitted as

logic [0] for valid commands.

RZ4 (D4)—This bit is used to enable an unconditional

RTZ event.

• 0 = Automatic Return to Zero

• 1 = Unconditional Return to Zero

RZ3 (D3)—This bit must be transmitted as logic [0] for

valid commands.

RZ2 (D2)—Return to Zero Direction bit. This bit is used to

properly sequence the integrator, depending upon the

desired zeroing direction.

• 0 = Return to Zero will occur in the CCW direction

(PE7 = 0)

• 1 = Return to Zero will occur in the CW direction

(PE7 = 1)

Table 9. Gauge 0 Position Register (POS0R)

Address 010

Bits

D12

D11

D10

Read

–

Write

P011

P010

P09

P08

P07

P06

P05

P04

P03

P02

P01

P00

Table 10. Gauge 1 Position Register (POS1R)

Address 011

Bits

D12

D11

D10

Read

–

Write

P111

P110

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

Table 11. Return to Zero Register (RTZR)

Address 100

Bits

D12

D11

D10

Read

–

Write

RZ4

RZ2

RZ1

RZ0

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