TDA4887PS datasheet(13/68 Pages) PHILIPS

13 / 68 page

2001 Oct 19

Philips Semiconductors

Product speciﬁcation

160 MHz bus-controlled monitor video

preampliﬁer

TDA4887PS

10 CHARACTERISTICS

All voltages and currents are measured in a dedicated test circuit (see Fig.17) optimized for best high frequency

performance; all voltages are measured with respect to GND (pins 9 and 14); VP =VP1,2,3 = 8 V (pins 7, 21, 18 and 15);

Tamb =25 °C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22,

19 and 16); reference black level (Vbl(ref)) approximately 0.7 V; nominal setting for brightness; maximum settings for

OSD contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (VLIM ≥ 5 V); no OSD fast blanking

(pin 1 connected to ground); notes 1 to 3; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage (pin 7)

7.6

8.0

8.8

VP(SO)

supply voltage threshold at

pin 7 at which signal outputs

are switched off

note 1

6.8

7.0

7.2

supply current (pin 7)

note 4

−

VP(n)

supply voltage; channels 1,

2 and 3 (pins 21, 18 and 15)

7.6

8.0

8.8

IP(n)

supply current; channels 1,

2 and 3 (pins 21, 18 and 15)

pins 22, 19 and 16

open-circuit;

Vbl(n)(ref) = 0.7 V;

notes 4 and 5

−

Input clamping and vertical blanking input, validation of buffered I2C-bus data (CLI; pin 5)

VCLI

input clamping and vertical

blanking input signal

notes 6 and 7

no vertical blanking,

no input clamping

−0.1

−

+1.2

vertical blanking,

no input clamping

1.6

−

2.6

input clamping,

no vertical blanking

3.5

−

ICLI

input current

VCLI =1V

−−0.2

−µA

pin 5 connected to ground;

note 8

−80

−45

−30

µA

VCLI = −0.1 V; note 8

−250

−135

−100

µA

tr/f5

rise/fall time for input

clamping pulse; disable for

vertical blanking

note 6; see Fig.7

−−

ns/V

tW(CLI)

width of input clamping

pulse

200

−−

tW(I2C)(valid)

width of vertical blanking

pulse for validation of

buffered I2C-bus data

leading and trailing edge

threshold VCLI = 1.4 V;

note 7

−−

µs

td(I2C)(valid)

delay between leading edge

of vertical blanking pulse

and validation of buffered

I2C-bus data

I2C-bus buffered mode

transmission completed;

leading edge threshold

VCLI = 1.4 V; note 7;

see Fig.7

−−

µs

TDA4887PS Datasheet(PDF) 13 Page - NXP Semiconductors

TDA4887PS Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL