TDA4887PS datasheet(23/68 Pages) PHILIPS

23 / 68 page

2001 Oct 19

Philips Semiconductors

Product speciﬁcation

160 MHz bus-controlled monitor video

preampliﬁer

TDA4887PS

26. Control bit FPOL = 0: the internal feedback reference voltages for DC control act under I2C-bus control; subaddress

07H (channel 1), 08H (channel 2) and 09H (channel 3); bit resolution 0.4% of voltage range. Rising values of the data

bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs

(pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs

(pins 23, 20 and 17) during output clamping (VHFB > 3.5 V) in closed feedback loop. The feedback loop remains

operative at reference black levels between the specified values of Vo(n)bl(ref)(min) and Vo(n)bl(ref)(max).

Control bit BRI = 1: the internal feedback reference voltages can be shifted under I2C-bus control which allows easy

brightness control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage

shift range). The superimposition of internal feedback reference and brightness control leads to a voltage output

range of 5.8 to 2.5 V.

27. Slow variations of video supply voltage VCRT will be suppressed at the CRT cathode by the clamping feedback loop.

A change of VCRT with 5 V leads to a specified change of the cathode voltage.

28. To adapt to different types of post amplifier, the internal feedback reference voltage for AC coupling (control bit

FPOL = 1) acts under I2C-bus control; subaddress 0AH (bit resolution 14.29%). The internal feedback reference

voltage can be measured at signal outputs (pins 22, 19 and 16) during output clamping (VHFB > 3.5 V); reference

black level or pedestal black level.

29. The DAC output voltages act under I2C-bus control for control bit FPOL = 1; subaddress 07H (FB/R1), 08H (FB/R2)

and 09H (FB/R3); bit resolution 0.4% of voltage range respectively. Using an inverting amplifier for DC restoration,

rising values of the data bytes, e.g. 00H to FFH, correspond to changing the light output from dark to bright.

With control bit BRI = 1 the DAC output voltages can be shifted under I2C-bus control which allows easy brightness

control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage shift range).

The superimposition of black level control and brightness control leads to a voltage output range of 5.8 to 2.5 V.

30. All adjustments via the I2C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I2C-bus

transmission in buffered mode. Conversely the adjustments via the I2C-bus will take effect immediately in

direct mode.

The timing of I2C-bus transmissions in buffered mode is related to the vertical blanking. See Section 7.6 and note 7

for specification of vertical blanking input (pin 5).

TDA4887PS Datasheet(PDF) 23 Page - NXP Semiconductors