H838024 datasheet(367/697 Pages) RENESAS

367 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 325 of 652

REJ09B0042-0700

IRQAEC Operation

When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC

is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and

ECL do not count. ECH and ECL count operations can therefore be controlled from outside by

controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.

IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector

addresses are H'000C and H'000D.

Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,

IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an

interrupt request is sent to the CPU.

Rising, falling, or both edge sensing can be selected for the IRQAEC input pin, with bits AIAGS1

and AIAGS0 in AEGSR.

Note:

On the H8/38124 Group, control of switching between the system clock oscillator and the

on-chip oscillator during resets should be performed by setting the IRQAEC input level.

Refer to section 4, Clock Pulse Generators, for details.

Event Counter PWM Operation

When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event

counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to

the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be

controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL

cannot be controlled individually.

IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the

vector addresses are H'000C and H'000D.

Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,

IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an

interrupt request is sent to the CPU.

Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits

AIAGS1 and AIAGS0 in AEGSR.

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