 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
H838024 Datasheet(PDF) 370 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H838024 Datasheet(HTML) 370 Page - Renesas Technology Corp |
|
|
370 / 697 page  Section 9 Timers Rev. 7.00 Mar 10, 2005 page 328 of 652 REJ09B0042-0700 9.7.4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9.21. Table 9.21 Asynchronous Event Counter Operation Modes Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby AEGSR Reset Functions Functions Retained* 1 Functions Functions Retained* 1 Retained ECCR Reset Functions Functions Retained* 1 Functions Functions Retained* 1 Retained ECCSR Reset Functions Functions Retained* 1 Functions Functions Retained* 1 Retained ECH Reset Functions Functions Functions* 1*2 Functions*2 Functions*2 Functions*1*2 Halted ECL Reset Functions Functions Functions* 1*2 Functions*2 Functions*2 Functions*1*2 Halted IRQAEC Reset Functions Functions Retained* 3 Functions Functions Retained* 3 Retained* 4 Event counter PWM Reset Functions Functions Retained Retained Retained Retained Retained Notes: 1. When an asynchronous external event is input, the counter increments but the counter overflow H/L flags are not affected. 2. Operates when asynchronous external events are selected; halted and retained otherwise. 3. Clock control by IRQAEC operates, but interrupts do not. 4. As the clock is stopped in module standby mode, IRQAEC has no effect. 9.7.5 Application Notes 1. When reading the values in ECH and ECL, the correct value will not be returned if the event counter increments during the read operation. Therefore, if the counter is being used in the 8- bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL. 2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and ensure that the high and low widths of the clock are at least half the OSC clock cycle duration. The duty cycle is immaterial. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
