H838024 datasheet(132/697 Pages) RENESAS

132 / 697 page

Section 3 Exception Handling

Rev. 7.00 Mar 10, 2005 page 90 of 652

REJ09B0042-0700

Wakeup Edge Select Register (WEGR)

Bit

Initial value

Read/Write

WKEGS7

R/W

WKEGS6

R/W

WKEGS5

R/W

WKEGS4

R/W

WKEGS3

R/W

WKEGS0

R/W

WKEGS2

R/W

WKEGS1

R/W

WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins

WKPn.

WEGR is initialized to H'00 by a reset.

Bit n—

WKPn Edge Select (WKEGSn)

Bit n selects

WKPn pin input sensing.

Bit n

WKEGSn

Description

WKPn pin falling edge detected

(initial value)

WKPn pin rising edge detected

(n = 7 to 0)

3.3.3

External Interrupts

There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC.

Interrupts WKP7 to WKP0

Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins

WKP

7 to

WKP

0. When these pins are designated as pins

WKP

7 to

WKP

0 in port mode register 5 and a

rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.

Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in

IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.

When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR.

Vector number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the

same vector number, so the interrupt-handling routine must discriminate the interrupt source.

H838024 Datasheet(PDF) 132 Page - Renesas Technology Corp

H838024 Datasheet(HTML) 132 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL