H838024 datasheet(128/697 Pages) RENESAS

128 / 697 page

Section 3 Exception Handling

Rev. 7.00 Mar 10, 2005 page 86 of 652

REJ09B0042-0700

Bits 1 and 0—IRQ1 and IRQ0 Interrupt Request Flags (IRRI1 and IRRI0)

Bit n

IRRIn

Description

Clearing conditions:

(initial value)

When IRRIn = 1, it is cleared by writing 0

Setting conditions:

When pin

IRQn is designated for interrupt input and the designated signal edge is

input

(n = 1 or 0)

Interrupt Request Register 2 (IRR2)

Bit

Initial value

Read/Write

IRRDT

R/(W)*

IRRAD

R/(W)*



IRRTG

R/(W)*

IRRTFH

R/(W)*

IRREC

R/(W)*

IRRTFL

R/(W)*

IRRTC

R/(W)*

Note:

* Only a write of 0 for flag clearing is possible

IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct

transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter

interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is

necessary to write 0 to clear each flag.

Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)

Bit 7

IRRDT

Description

Clearing conditions:

(initial value)

When IRRDT = 1, it is cleared by writing 0

Setting conditions:

When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in

SYSCR2

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