H838024 datasheet(124/697 Pages) RENESAS

124 / 697 page

Section 3 Exception Handling

Rev. 7.00 Mar 10, 2005 page 82 of 652

REJ09B0042-0700

Bit 2—IRQAEC Interrupt Enable (IENEC2)

Bit 2 enables or disables IRQAEC interrupt requests.

Bit 2

IENEC2

Description

Disables IRQAEC interrupt requests

(initial value)

Enables IRQAEC interrupt requests

Bits 1 and 0—IRQ1 and IRQ0 Interrupt Enable (IEN1 and IEN0)

Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests.

Bit n

IENn

Description

Disables interrupt requests from pin

IRQn

(initial value)

Enables interrupt requests from pin

IRQn

(n = 1 or 0)

Interrupt Enable Register 2 (IENR2)

Bit

Initial value

Read/Write

IENDT

R/W

IENAD

R/W

—

IENTG

R/W

IENTFH

R/W

IENEC

R/W

IENTFL

R/W

IENTC

R/W

IENR2 is an 8-bit read/write register that enables or disables interrupt requests.

Bit 7—Direct Transfer Interrupt Enable (IENDT)

Bit 7 enables or disables direct transfer interrupt requests.

Bit 7

IENDT

Description

Disables direct transfer interrupt requests

(initial value)

Enables direct transfer interrupt requests

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