H838024 datasheet(123/697 Pages) RENESAS

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Section 3 Exception Handling

Rev. 7.00 Mar 10, 2005 page 81 of 652

REJ09B0042-0700

Interrupt Enable Register 1 (IENR1)

Bit

Initial value

Read/Write

IENTA

R/W



IENWP

R/W

IEN4

R/W

IEN3

R/W

IEN0

R/W

IENEC2

R/W

IEN1

R/W

IENR1 is an 8-bit read/write register that enables or disables interrupt requests.

Bit 7—Timer A Interrupt Enable (IENTA)

Bit 7 enables or disables timer A overflow interrupt requests.

Bit 7

IENTA

Description

Disables timer A interrupt requests

(initial value)

Enables timer A interrupt requests

Bit 6—Reserved

Bit 6 is reserved: it can only be written with 0.

Bit 5—Wakeup Interrupt Enable (IENWP)

Bit 5 enables or disables WKP7 to WKP0 interrupt requests.

Bit 5

IENWP

Description

Disables

WKP7 to WKP0 interrupt requests

(initial value)

Enables

WKP7 to WKP0 interrupt requests

Bits 4 and 3—IRQ4 and IRQ3 Interrupt Enable (IEN4 and IEN3)

Bits 4 and 3 enable or disable IRQ4 and IRQ3 interrupt requests.

Bit n

IENn

Description

Disables interrupt requests from pin

IRQn

(initial value)

Enables interrupt requests from pin

IRQn

(n = 4 or 3)

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