H838024 datasheet(292/697 Pages) RENESAS

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Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 250 of 652

REJ09B0042-0700

Timer Counter A (TCA)

Bit

Initial value

Read/Write

TCA7

TCA6

TCA5

TCA4

TCA3

TCA0

TCA2

TCA1

TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock

source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A

(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive

mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.

TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.

Upon reset, TCA is initialized to H'00.

Clock Stop Register 1 (CKSTPR1)



TFCKSTP TCCKSTP TACKSTP



S32CKSTP ADCKSTP TGCKSTP

543210

1111111



R/W



R/W

Bit:

Initial value:

Read/Write:

CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral

modules. Only the bit relating to timer A is described here. For details of the other bits, see the

sections on the relevant modules.

Bit 0—Timer A Module Standby Mode Control (TACKSTP)

Bit 0 controls setting and clearing of module standby mode for timer A.

TACKSTP

Description

Timer A is set to module standby mode

Timer A module standby mode is cleared

(initial value)

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