H838024 datasheet(293/697 Pages) RENESAS

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Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 251 of 652

REJ09B0042-0700

9.2.3

Timer Operation

Interval Timer Operation

When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit

interval timer.

Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval

timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in

TMA; any of eight internal clock signals output by prescaler S can be selected.

After the count value in TCA reaches H'FF, the next clock signal input causes timer A to

overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt

enable register 1 (IENR1), a CPU interrupt is requested.*

At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as

an interval timer that generates an overflow output at intervals of 256 input clock pulses.

Note: * For details on interrupts, see section 3.3, Interrupts.

Real-Time Clock Time Base Operation

When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting

clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and

TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting

bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.

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