CS42526 datasheet(56/93 Pages) CIRRUS

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DS585F1

CS42526

6.9.3

SYSTEM CLOCK SELECTION (ACTIVE_CLK)

Default = x

0 - Output of PLL

1 - OMCK

Function:

This bit identifies the source of the internal system clock (MCLK).

6.9.4

RECEIVER CLOCK FREQUENCY (RCVR_CLKX)

Default = xxx

Function:

The CS42526 detects the ratio between the OMCK and the recovered clock from the PLL. Given the

absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL

clock.

If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX

bits are set accordingly (see “OMCK Frequency (OMCK Freqx)” on page 53), the absolute frequency

of the PLL clock is reflected in the RCVR_CLKX bits according to Table 16. If the absolute frequency

of the PLL clock does not match one of the frequencies given in Table 16, these bits will reflect the

closest available value.

If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents

of the RCVR_CLKX bits will be inaccurate and should be disregarded. In this case, an external con-

troller may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to

determine the absolute frequency of the PLL clock.

Note:

These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.

6.10

Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only)

6.10.1 BURST PREAMBLE BITS (PCX & PDX)

Default = xxh

Function:

The PC and PD burst preamble bytes are loaded into these four registers.

RCVR_CLK2 RCVR_CLK1 RCVR_CLK0

Description

8.1920 MHz

11.2896 MHz

12.288 MHz

16.3840 MHz

22.5792 MHz

24.5760 MHz

45.1584 MHz

49.1520 MHz

Table 14. Receiver Clock Frequency Detection

543

PCx-7

PCx-6

PCx-5

PCx-4

PCx-3

PCx-2

PCx-1

PCx-0

PDx-7

PDx-6

PDx-5

PDx-4

PDx-3

PDx-2

PDx-1

PDx-0

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