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PM4332 Datasheet(PDF) 39 Page - PMC-Sierra, Inc |
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PM4332 Datasheet(HTML) 39 Page - PMC-Sierra, Inc |
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39 / 446 page ![]() PRELIMINARY PM4332 TE-32 DATA SHEET PMC-2011402 ISSUE 1 HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS 30 Pin Name Type Pin No. Function LDC1FP Input AB6 Line Drop C1 Frame Pulse (LDC1FP). The LDC1FP provides frame synchronization for devices connected via an SBI interface. LDC1FP is asserted, for one LREFCLK cycle, for the first C1 byte of the SBI multiframe on the LDDATA[7:0] bus. This signal occurs every 500 µS (i.e. every 9720 LREFCLK cycles). LDC1FP is sampled on the rising edge of LREFCLK. LDV5 Input W6 Line Drop Bus V5 Byte (LDV5). The incoming tributary V5 byte signal marks the various tributary V5 bytes. LDV5 marks each tributary V5 byte on the LDDATA[7:0] bus when high. LDV5 is sampled on the rising edge of LREFCLK. LDPL Input Y8 Line Drop Bus Tributary Payload Active (LDPL). The tributary payload active signal marks the bytes carrying the tributary payload which have been identified by an external payload processor. When this signal is available, the internal pointer processor can be bypassed. LDPL is only respected for asynchronously mapped tributaries. LDPL is high during each tributary payload byte on the LDDATA[7:0] bus. LDPL is sampled on the rising edge of LREFCLK. |
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