PM4332 datasheet(71/446 Pages) PMC

71 / 446 page

PRELIMINARY

PM4332 TE-32

DATA SHEET

PMC-2011402

ISSUE 1

HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS

The transmitter provides per-channel control of idle code substitution, data

inversion (either all 8 bits, sign bit magnitude or magnitude only), and zero code

suppression. Three types of zero code suppression (GTE, Bell and "jammed bit

8") are supported and selected on a per-channel basis to provide minimum ones

density control. Context bits provide per-channel control of robbed bit signaling

and selection of the signaling source. All channels can be forced into a trunk

conditioning state by the Master Trunk Conditioning (MTRK) context bit. The

transmitter may source pseudo-random bit sequences (PRBS) in a selected sub-

set of channels, while simultaneously monitoring the data from the system

interface for PRBS errors.

A data link is provided for ESF mode. The data link sources include bit oriented

codes and HDLC messages. If the T1_FDL_DIS context bit is logic 1, the data

link is sourced from the F-bit position of the H-MVIP or SBI interface. Support is

provided for the transmission of framed or unframed Inband Code sequences

and transmission of AIS, Yellow, AIS-CI and RAI-CI (ESF only) alarm signals for

all formats.

If the AUTOUPDATE bit of the T1/E1 Framer Configuration and Status register is

logic 1, the T1 transmitter automatically sends an ANSI T1.403-formatted

performance report on the T1 facility data link once per second.

The F-bit may be passed transparently from either the H-MVIP or SBI interface.

To support alignment of the robbed bit signaling to the F-bits, the C8MVFPB input

may be redefined as a superframe alignment pulse.

The transmitter can be disabled for framing via the FDIS context bit.

9.8.1 SLC



96

SLC

96 is partially supported. The F-bits must be sourced from the system

interface. To pass the F-bits transparently, the FDIS context bit must be set.

Also, a superframe alignment must be provided to ensure the robbed-bit

signaling is inserted in the correct frames relative to the F-bits. To ensure the

framing is not corrupted, the timing must be configured to avoid controlled frame

slips.

When using the SBI interface, it is recommended the transmit frame slip buffer be

bypassed and that the transmit clock be locked to the data stream (i.e. TJAT

LOOPT and REFSEL context bits logic 0).

With an H-MVIP interface, the transmit elastic store cannot be bypassed, so the

transmit clock must be locked to CTCLK which must be presented a clock that is

locked to CMV8MCLK.

PM4332 Datasheet(PDF) 71 Page - PMC-Sierra, Inc

PM4332 Datasheet(HTML) 71 Page - PMC-Sierra, Inc

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