PM4332 datasheet(40/446 Pages) PMC

40 / 446 page

PRELIMINARY

PM4332 TE-32

DATA SHEET

PMC-2011402

ISSUE 1

HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS

Pin Name

Type

No.

Function

SBI System Side Interface

CTCLK

Input

F19

Common Transmit Clock (CTCLK). This input

signal is used as a reference transmit tributary

clock which can be used in egress Clock Master

modes. CTCLK must be multiple of 8 kHz. The

transmit clock is derived by the jitter attenuator

PLL using CTCLK as a reference.

The TE-32 may be configured to ignore the

CTCLK input and lock to the data or one of the

recovered Ingress clocks instead, RECVCLK1,

RECVCLK2 and RECVCLK3. The receive

tributary clock is automatically substituted for

CTCLK if line loopback or looptiming is enabled.

S77/MVED[3]

Input

D10

System Side SBI 77.76 MHz Select (S77). This

input determines the frequency of SREFCLK. If

S77 is low, SREFCLK is expected to be

19.44MHz. If S77 is high, SREFCLK is expected

to be 77.76 MHz and data is driven and sampled

every fourth cycle.

This signal is a don’t care when the

SYSOPT[1:0] register bits are binary “01” (H-

MVIP inteface). In this mode SREFCLK is

required to be 19.44 MHz.

S77 is expected to be held static.

S77 shares the same pin as MVED[3]. S77 is

selected when the SYSOPT[1:0] bits are set to

“10” or “11”, in the Global Configuration register.

SREFCLK

Input

C10

System Reference Clock (SREFCLK). This

system reference clock is a nominal 19.44 MHz

+/-50ppm pr 77.76 MHz +/-50ppm 50% duty

cycle clock. This clock is common to both the add

and drop sides of the SBI bus.

SREFCLK must be active for all applications.

When the SYSOPT[1:0] register bits are binary

“01” (H-MVIP interface), SREFCLK is required to

be 19.44 MHz.

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