PM4332 datasheet(79/446 Pages) PMC

79 / 446 page

PRELIMINARY

PM4332 TE-32

DATA SHEET

PMC-2011402

ISSUE 1

HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS

9.12 T1/E1 Pseudo Random Binary Sequence Generation and Detection (PRBS)

The Pseudo Random Binary Sequence Generator/Detector (PRBS) is a software

selectable PRBS generator and checker for 27-1, 211-1, 215-1 or 220-1 PRBS

polynomials for use in the T1 and E1 links. PRBS patterns may be generated

and monitored in both the transmit or receive directions for all T1 and E1 links

simultaneously. The generator is capable of inserting single bit errors under

microprocessor control.

The detector auto-synchronizes to the expected PRBS pattern and accumulates

the total number of bit errors in a 16-bit counter. The error count accumulates

over the interval defined by writes to the Global PMON Update register. When a

transfer is triggered, the holding register is updated, and the counter reset to

begin accumulating for the next interval. The counter is reset in such a way that

no events are missed. The data is then available until the next transfer.

In addition to the basic PRBS generators and receivers associated with each

T1/E1 link, six full featured generator/receiver pairs are available for association

with any software selectable link. Any subset of bits within a frame (except the

T1 F-bit) may be programmed to carry either a pseudo-random or fixed pattern.

The six generators can be programmed to generate any pseudo-random pattern

with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits

in length. It also can generate the four DDS codes specified by Bellcore GR-819-

CORE. In addition, the PRGD can insert single bit errors or a bit error rate

between 10-1 to 10-7.

The six receivers can be programmed to check for the generated pseudo random

pattern. The receivers can perform an auto synchronization to the expected

pattern and accumulates the total number of bits received and the total number of

bit errors in two 32-bit counters. The counters accumulate either over intervals

defined by writes to the Pattern Detector registers or upon writes to the Global

PMON Update Register. When a transfer is triggered, the holding registers are

updated, and the counters reset to begin accumulating for the next interval. The

counters are reset in such a way that no events are missed. The data is then

available in the holding registers until the next transfer.

9.13 Egress H-MVIP System Interface

The Egress H-MVIP System Interface (Figure 11) provides system side H-MVIP

access for up to 32 T1 or E1 transmit streams. There are three separate

interfaces for data, CAS signaling and CCS signaling. The H-MVIP signaling

interfaces can be used in combination with the SBI interface in certain

applications. Control of the system side interface is global to TE-32 and is

PM4332 Datasheet(PDF) 79 Page - PMC-Sierra, Inc

PM4332 Datasheet(HTML) 79 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL