STAC9766 datasheet(28/97 Pages) IDT

28 / 97 page

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

PC AUDIO

IDT™

STAC9766/9767

V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

5.2.

AC-link Serial Interface Protocol

The AC‘97 Controller signals synchronization of all AC-link data transactions. The AC‘97 CODEC,

Controller, or external clock source drives the serial bit clock (BIT_CLK) onto the AC-link, which the

AC‘97 Controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed

at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz,

provides the necessary clocking granularity to support twelve 20-bit outgoing and incoming time

slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link

data (CODEC for outgoing data and Controller for incoming data) samples each serial bit on the fall-

ing edges of BIT_CLK.

The AC-link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid

tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0

indicates that the corresponding time slot within the current audio frame has been assigned to a data

stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the

data, (AC‘97 CODEC for the input stream, AC‘97 Controller for the output stream), to stuff all bit

positions with 0 during that slot’s active time.

SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The

portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the

audio frame where SYNC is low is defined as the “Data Phase”.

Additionally, for power savings, BIT_CLK, SYNC, and all data signals can be halted. This requires

that an AC‘97 CODEC be implemented as a static design to allow its register contents to remain

intact when entering a power savings mode.

5.2.1.

AC-link Variable Sample Rate Operation

The AC-link serial interconnect defines a digital data and control pipe between the Controller and the

CODEC. The AC-link supports twelve 20-bit slots at 48 KHz on SDATA_IN and SDATA_OUT. The

time division multiplexed (TDM) “slot-based” architecture supports a per-slot valid tag infrastructure

that the source of each slot’s data sets or clears to indicate the validity of the slot data within the cur-

rent audio frame. This tag infrastructure can be used to support transfers between Controller and

CODEC at any sample rate.

Table 5. The AC-link input slots (transmitted from the CODEC)

Slot

Name

Description

SDATA_IN TAG

MSBs indicate which slots contain valid data

STATUS ADDR read port

MSBs echo register address; LSBs indicate which slots request data

STATUS DATA read port

16-bit command register read data

3, 4

PCM L&R ADC record

20-bit PCM data from Left and Right inputs

Modem Line 1 ADC

16-bit modem data from modem Line1 input

6-11

PCM ADC Record

20-bit PCM data - Alternative Slots for Input

GPIO Status

GPIO read port and interrupt status

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