STAC9766 datasheet(29/97 Pages) IDT

29 / 97 page

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

PC AUDIO

IDT™

STAC9766/9767

V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

5.2.2.

Variable Sample Rate Signaling Protocol

AC-link’s tag infrastructure imposes FIFO requirements on both sides of the AC-link. For example, in

passing a 44.1 KHz stream across the AC-link, for every 480 audio output frames that are sent

across, 441 of them must contain valid sample data. Does the AC‘97 Digital Controller pass all 441

PCM samples followed by 39 invalid slots? Or does the AC‘97 Digital Controller evenly interleave

valid and non-valid slots? Each possible method brings with it different FIFO requirements. To

achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different man-

ufacturers, it is necessary to standardize the scheme for at least one side of the AC-link so that the

FIFO requirements will be common to all designs. The CODEC side of the AC-link is the focus of this

standardization.

The new standard approach calls for the addition of “on demand” slot request flags. These flags are

passed from the CODEC to the AC‘97 Digital Controller during every audio input frame. Each time

the AC‘97 Digital Controller sees one or more of the newly-defined slot request flags set active (low)

in a given audio input frame, it knows that it must pass along the next PCM sample for the corre-

sponding slot(s) in the AC-link output frame that immediately follows.

The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to

1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions:

Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate

Registers 2C-34h.

Enables the on-demand CODEC-to-Controller signaling protocol using SLOTREQ bits that

becomes necessary when a DACs sample rate varies from the 48 KHz AC-link serial frame rate

The table below summarizes the behavior:

Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should

NOT be used.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-link output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current

AC-link input frame signal which active output slots require data from the AC‘97 Digital Controller in

the next audio output frame. An active output slot is defined as any slot supported by the CODEC

that is not in a power-down state. For fixed 48 KHz operation the SLOTREQ bits are always set

active (low) and a sample is transferred in each frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame.

Table 6. VRA Behavior

AC‘97 Functionality

VRA = 0

VRA = 1

SLOTREQ bits

always 0 (data each frame)

0 or 1 (data on demand)

sample rate registers

forced to 48 KHz

writable

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