STAC9766 datasheet(57/97 Pages) IDT

57 / 97 page

STAC9766/9767

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

PC AUDIO

IDT™

STAC9766/9767

V 7.4 12/06

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

The three separation ratios are implemented. The separation ratio defines a series of equations that

determine the amount of depth difference (High, Medium, and Low) perceived during two-channel

playback. The ratios provide for options to narrow or widen the soundstage.

8.1.17.

Audio Interrupt and Paging (24h)

Default: 0000h

D15

D14

D13

D12

D11

D10

RESERVED

PG3

PG2

PG1

PG0

Bit(s) Reset Value

Access

Name

Description

Read / Write

0 = Interrupt is clear

1 = Interrupt is set

Interrupt event is cleared by writing a 1 to this bit.

The interrupt bit will change regardless of condition of interrupt

enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink

will follow this bit change when interrupt enable (I0) is unmasked.

14-13

Read Only

I3-I2

Interrupt Cause

00 = Reserved

01 = Sense cycle complete, sense info available.

10 = Change in GPIO input status

11 = Sense cycle complete and change in GPIO input status.

These bits will reflect the general cause of the first interrupt event

generated. It should be read after interrupt status has been

confirmed as interrupting. The information should be used to scan

possible interrupting events in proper pages.

Read / Write

Sense Cycle

0 = Sense Cycle not in Progress

1 = Sense Cycle Start.

Writing a 1 to this bit causes a sense-cycle start, if supported. If

sense cycle is not supported, this bit is read only.

Read / Write

Interrupt Enable

0 = Interrupt generation is masked.

1 = Interrupt generation is un-masked.

The driver should not un-mask the interrupt unless ensured by the

AC‘97 controller that no conflict is possible with modem slot 12 -

GPI functionality. Some AC’97 2.2 compliant controllers will not

likely support audio CODEC interrupt infrastructure. In either case,

software should poll the interrupt status after initiating a sense

cycle and wait for Sense Cycle Max Delay to determine if an

interrupting event has occurred.

STAC9766 Datasheet(PDF) 57 Page - Integrated Device Technology

STAC9766 Datasheet(HTML) 57 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

Datasheet Download

Link URL