Electronic Components Datasheet Search
  English  ▼

X  

STAC9220 Datasheet(PDF) 46 Page - Integrated Device Technology

Part # STAC9220
Description  8-CHANNEL HIGH DEFINITION AUDIO CODEC
PDF  172 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

STAC9220 Datasheet(HTML) 46 Page - Integrated Device Technology

Back Button STAC9220 Datasheet HTML 42Page - Integrated Device Technology STAC9220 Datasheet HTML 43Page - Integrated Device Technology STAC9220 Datasheet HTML 44Page - Integrated Device Technology STAC9220 Datasheet HTML 45Page - Integrated Device Technology STAC9220 Datasheet HTML 46Page - Integrated Device Technology STAC9220 Datasheet HTML 47Page - Integrated Device Technology STAC9220 Datasheet HTML 48Page - Integrated Device Technology STAC9220 Datasheet HTML 49Page - Integrated Device Technology STAC9220 Datasheet HTML 50Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 46 / 172 page
background image
STAC9220/9221/9223
8-CHANNEL HIGH DEFINITION AUDIO CODEC
PC AUDIO
IDT™
46
STAC9220/9221/9223
V 0.96 102706
8-CHANNEL HIGH DEFINITION AUDIO CODEC
6.5.15.
AFG GPIOEn
[1]
Data1
RW
0x0
Data for GPIO1 (Pin 46). If this GPIO bit is
configured as Sticky (edge-sensitive) input, it can
be cleared by writing zero (one) here when the
corresponding Polarity Control bit is zero (one).
[0]
Data0
RW
0x0
Data for GPIO0 (Pin 45). If this GPIO bit is
configured as Sticky (edge-sensitive) input, it can
be cleared by writing zero (one) here when the
corresponding Polarity Control bit is zero (one).
Table 40. AFG GPIOEn Command Verb Format
Verb ID
Payload
Response
Get
F16
00
See bitfield table
Set1
716
See bits [7:0] of bitfield table
0000_0000h
Table 41. AFG GPIOEn Command Response Format
Bit
Bitfield Name
RW
Reset
Description
[31:4]
Rsvd
R
0x0
Reserved
[3]
Mask3
RW
0x0
Enable for GPIO3:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
[2]
Mask2
RW
0x0
Enable for GPIO2:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
[1]
Mask1
RW
0x0
Enable for GPIO1:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
[0]
Mask0
RW
0x0
Enable for GPIO0:
0 = pin is disabled (Hi-Z state);
1 = pin is enabled; behavior determined by
GPIO Direction control
Table 39. AFG GPIO Command Response Format
Bit
Bitfield Name
RW
Reset
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com