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STAC9220 Datasheet(PDF) 46 Page - Integrated Device Technology |
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STAC9220 Datasheet(HTML) 46 Page - Integrated Device Technology |
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46 / 172 page ![]() STAC9220/9221/9223 8-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 46 STAC9220/9221/9223 V 0.96 102706 8-CHANNEL HIGH DEFINITION AUDIO CODEC 6.5.15. AFG GPIOEn [1] Data1 RW 0x0 Data for GPIO1 (Pin 46). If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing zero (one) here when the corresponding Polarity Control bit is zero (one). [0] Data0 RW 0x0 Data for GPIO0 (Pin 45). If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing zero (one) here when the corresponding Polarity Control bit is zero (one). Table 40. AFG GPIOEn Command Verb Format Verb ID Payload Response Get F16 00 See bitfield table Set1 716 See bits [7:0] of bitfield table 0000_0000h Table 41. AFG GPIOEn Command Response Format Bit Bitfield Name RW Reset Description [31:4] Rsvd R 0x0 Reserved [3] Mask3 RW 0x0 Enable for GPIO3: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control [2] Mask2 RW 0x0 Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control [1] Mask1 RW 0x0 Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control [0] Mask0 RW 0x0 Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control Table 39. AFG GPIO Command Response Format Bit Bitfield Name RW Reset Description |
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