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TDA4VM21 Datasheet(PDF) 103 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 103 Page - Texas Instruments |
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103 / 331 page  Table 5-75. EHRPWM5 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM_TZn_IN5 EHRPWM Trip Zone Input 5 (active low) I W25 5.3.15 USB 5.3.15.1 MAIN Domain Note USB3 functionality is available on the SERDES pins. For more information, refer to Section 5.3.16, SERDES. Table 5-76. USB0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] USB0_DM USB 2.0 Differential Data (negative) IO AJ5 USB0_DP USB 2.0 Differential Data (positive) IO AH6 USB0_DRVVBUS USB VBUS control output (active high) O T25, T26, U6, V4, W3 USB0_ID USB 2.0 Dual-Role Device Role Select A AC6 USB0_RCALIB (2) Pin to connect to calibration resistor A AB6 USB0_VBUS (1) USB Level-shifted VBUS Input A AC7 (1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.3.4, USB Design Guidelines. (2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused. Table 5-77. USB1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] USB1_DM USB 2.0 Differential Data (negative) IO AH7 USB1_DP USB 2.0 Differential Data (positive) IO AJ6 USB1_DRVVBUS USB VBUS control output (active high) O T25, T26, U6, V4, W3 USB1_ID USB 2.0 Dual-Role Device Role Select A AD7 USB1_RCALIB (2) Pin to connect to calibration resistor A AD9 USB1_VBUS (1) USB Level-shifted VBUS Input A AD8 (1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.3.4, USB Design Guidelines. (2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused. 5.3.16 SERDES 5.3.16.1 MAIN Domain Table 5-78. SERDES0 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE0_CLKREQn PCIE Clock Request Signal IO W2 PCIE_REFCLK0N PCIE Reference Clock Input/Output (negative) IO AE17 PCIE_REFCLK0P PCIE Reference Clock Input/Output (positive) IO AD16 SERDES0_REXT (1) External Calibration Resistor A AE18 SERDES0_RX0_N SERDES Differential Receive Data (negative) I AH19 SERDES0_RX0_P SERDES Differential Receive Data (positive) I AJ18 SERDES0_RX1_N SERDES Differential Receive Data (negative) I AH18 SERDES0_RX1_P SERDES Differential Receive Data (positive) I AJ17 www.ti.com TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: TDA4VM-Q1 TDA4VM |
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