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TDA4VM21 Datasheet(PDF) 104 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 104 Page - Texas Instruments |
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104 / 331 page  Table 5-78. SERDES0 Signal Descriptions (continued) SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES0_TX0_N SERDES Differential Transmit Data (negative) O AF19 SERDES0_TX0_P SERDES Differential Transmit Data (positive) O AG18 SERDES0_TX1_N SERDES Differential Transmit Data (negative) O AF18 SERDES0_TX1_P SERDES Differential Transmit Data (positive) O AG17 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES0_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-79. SERDES1 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE1_CLKREQn PCIE Clock Request Signal IO W1 PCIE_REFCLK1N PCIE Reference Clock Input/Output (negative) IO AE14 PCIE_REFCLK1P PCIE Reference Clock Input/Output (positive) IO AD15 SERDES1_REXT (1) External Calibration Resistor A AE13 SERDES1_RX0_N SERDES Differential Receive Data (negative) I AH15 SERDES1_RX0_P SERDES Differential Receive Data (positive) I AJ14 SERDES1_RX1_N SERDES Differential Receive Data (negative) I AH16 SERDES1_RX1_P SERDES Differential Receive Data (positive) I AJ15 SERDES1_TX0_N SERDES Differential Transmit Data (negative) O AF15 SERDES1_TX0_P SERDES Differential Transmit Data (positive) O AG14 SERDES1_TX1_N SERDES Differential Transmit Data (negative) O AF16 SERDES1_TX1_P SERDES Differential Transmit Data (positive) O AG15 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES1_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-80. SERDES2 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE2_CLKREQn PCIE Clock Request Signal IO P23 PCIE_REFCLK2N PCIE Reference Clock Input/Output (negative) IO AE11 PCIE_REFCLK2P PCIE Reference Clock Input/Output (positive) IO AD12 SERDES2_REXT (1) External Calibration Resistor A AD13 SERDES2_RX0_N SERDES Differential Receive Data (negative) I AH13 SERDES2_RX0_P SERDES Differential Receive Data (positive) I AJ12 SERDES2_RX1_N SERDES Differential Receive Data (negative) I AH12 SERDES2_RX1_P SERDES Differential Receive Data (positive) I AJ11 SERDES2_TX0_N SERDES Differential Transmit Data (negative) O AF13 SERDES2_TX0_P SERDES Differential Transmit Data (positive) O AG12 SERDES2_TX1_N SERDES Differential Transmit Data (negative) O AF12 SERDES2_TX1_P SERDES Differential Transmit Data (positive) O AG11 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES2_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-81. SERDES3 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE3_CLKREQn PCIE Clock Request Signal IO R28 TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 www.ti.com 104 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VM-Q1 TDA4VM |
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