TDA4VM21 datasheet(173/331 Pages) TI

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J7ES_ELCH_01

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,

VDDSHV4, VDDSHV5 , VDDSHV6) , VDDA_3P3_USB

(4)

(2)

(5)

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV1, VDDSHV2,

VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDS_MMC0

(4)

(3)

(7)

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV1, VDDSHV2,

VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDS_MMC0

(4)

(3)

(7)

VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,

VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP,

VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1,

VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,

VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3

VDD_CPU

VDD_MCU , VDD_CORE, (VDDA_0P8_SERDES0_1,

(8)

VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,

VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,

VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,

VDDA_0P8_DSITX, VDDA_0P8_DSITX_C)

(9)

, VDDAR_CORE, VDDAR_CPU, VDDAR_MCU

PORz, MCU_PORz

(11)(12)

WKUP_OSC0_XI, WKUP_OSC1_XO

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

OSC1_XI, OSC1_XO

(optional)

VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB

(10)

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

(11)

Valid Configuration

(VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,

VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,

VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3)

(6)

VDD_MCU

(8)

Note 2

Figure 6-3. Combined MCU and Main Domains, Primary Power-Up Sequence

1. Time Stamp Markers

T0 – 3.3V voltages start ramp-up to VOPR MIN. (0ms)

T1 – 1.8V voltages start ramp-up to VOPR MIN. (2ms)

T2 – Low voltage core supplies start ramp-up to VOPR MIN. (3ms)

T3 – Low voltage RAM array voltages start ramp-up to VOPR MIN. (4ms)

T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13ms)

2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to

support 3.3V digital interfaces. A few supplies could have varying start times between T0 to T1 due to PDN

designs using different power resources with varying turn-on & ramp-up time delays.

3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to

support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp-up

aligned to T3 due to PDN designs grouping supplies with VDD_MMC0.

4. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant high-speed SD card operation is

needed, then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of

ramp-up to 3.3V will be same as other 3.3V domains as shown. If SD card is not needed or standard data

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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