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4. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required

for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then

an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from

3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates

with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD

card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.

5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,

analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start

of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or

data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or

through a supply filter.

6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog

supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of

these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains

can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.

7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at

time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V

can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or

eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down

at time stamp T3.

8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,

enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM

array domains (VDDAR_xxx) at time stamp T1.

9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry

needing a low noise supply for optimal performance. It is not recommended to combine analog

VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency

switching noise could negatively impact jitter performance of clock, PLL and DLL signals.

10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe

state before any voltage begins to ramp down.

6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing

Isolated MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate

independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main

processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce

SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain

freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which

is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of

additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels.

If only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO

signaling is desired, then 4 additional power rails could be needed. Table 8-2 in Section 8.1, Power Supply

Mapping captures recommended device power supplies to power rail mapping summary.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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