TDA4VM21 datasheet(172/331 Pages) TI

172 / 331 page

6.9.2 Power Supply Sequencing

This section describes power supply sequencing required to ensure proper device operation. The device can be

operated using either an isolated or combined MCU & Main power distribution network (PDN). Two different

primary power sequences are recommended based upon isolated and combined MCU & Main PDNs. In

addition, the device can be operated in either MCU Only or DDR Retention low power modes. Two different

desired device power supply sequences for entry and exit of low power modes are shown.

The power supply names used in this section are specific to this device and align to names given in the Signal

Descriptions section. Common power supply names may be used across different devices within the Jacinto 7TM

processor family. These common supply names will have very similar if not identical functions across devices.

All power sequencing timing diagrams shown will use the following terminology:

• Primary = Essential power sequences of all voltage domains between off and full active states.

• VOPR MIN = Minimum operational voltage level that ensures functionality as specified in Recommended

Operating Conditions

• Ramp-up = start of a voltage supply transition time from off condition to Vopr min.

• Ramp-down = start of a voltage supply transition time from Vopr to off condition

• Supply_“n” = multiple instances of similar power supplies (i.e. VDDSHVn = VDDSHV0, VDDSHV1,

VDDSHV2 … VDDSHV6)

• Supply_“xxx” = multiple instances of similar power supplies used for different signal types (i.e.

VDDA_1P8_xxx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)

• Time stamps = “T#” markers with descriptions and approximate elapsed times for general reference. Specific

timing transitions are dependent upon PDN design (see PDN User Guide for details).

6.9.2.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the

maximum slew rate of supplies to be less than 100 mV/us, as shown in Figure 6-2. For instance, a 1.8V supply

should have a ramp time > 18 μs to ensure the slew rate < 100mV/us.

Figure 6-2 describes the Power Supply Slew Rate Requirement in the device.

Supply value

SPRSP08_ELCH_06

Slew Rate = ∆V / ∆T

Max Slew Rate < 100 mV / µs or 0.1 V / 1E(-6)s = 1E(+5) V / s

∆Tmin > ∆V / Max Slew Rate or 1.8 V / 1E(+5) V / s

∆Tmin > 18 µs

Figure 6-2. Power Supply Slew and Slew Rate

6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing

Figure 6-3 describes the primary power-up sequencing when similar MCU and Main voltage domains are

combined into common power rails. Combining MCU and Main voltage domains simplifies PDN design by

reducing total number of power rails and sources while making MCU and Main processor sub-systems

operational dependent on common power rails. Table 8-1 in Section 8.1, Power Supply Mapping captures

recommended device power supply groups to power rail mapping summary.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

172

Submit Document Feedback

Product Folder Links: TDA4VM-Q1 TDA4VM

TDA4VM21 Datasheet(PDF) 172 Page - Texas Instruments

TDA4VM21 Datasheet(HTML) 172 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL