TDA4VM21 datasheet(168/331 Pages) TI

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Note

The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3

Clause 70.

Note

The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.

Note

The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.

This Device imposes an additional limit on the 2-L-PHY SERDES REFCLK, as described by parameters VIDTH

and VIDTL in Table 6-11, 2-L-PHY SERDES REFCLK Electrical Characteristics.

Table 6-11. 2-L-PHY SERDES REFCLK Electrical Characteristics

Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

BALL NAMES in Mode 0: PCIE_REFCLK[3:0]P, PCIE_REFCLK[3:0]N

BALL NUMBERS:AE9 / AD10 / AE11 / AD12 / AE14 / AD15 / AE17 / AD16

VIDTH

Input Differential high-level threshold

200

VIDTL

Input Differential low-level threshold

–200

UFS M-PHY Electrical Characteristics

Note

The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1,

February 17, 2014.

eDP/DP AUX-PHY Electrical Characteristics

Note

The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v

1.4 February 23, 2016.

Note

The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort

(eDP) Standard v1.4b October 23, 2015.

DDR0 Electrical Characteristics

Note

The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.

6.7 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses and is applicable only

for High-Security Devices.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

168

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