TDA4VM21 datasheet(167/331 Pages) TI

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Table 6-9. LVCMOS Electrical Characteristics (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER(1)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

2.4

IOL (2)

Low Level Output Current

VOL(MAX)

IOH (2)

High Level Output Current

VOH(MIN)

SRI (4)

Input Slew Rate

33f(3)

3.3E+6

V/s

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section

5.2, Pin Attributes, POWER column.

(2)

The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is

able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current

available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.

(3)

f = toggle frequency of the input signal in Hz.

(4)

This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching

Characteristics sections. Select the MIN parameter which results in the largest value.

USB2PHY Electrical Characteristics

Note

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0

Specification dated April 27, 2000 including ECNs and Errata as applicable.

SerDes 4-L-PHY/2-L-PHY Electrical Characteristics

Note

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base

Specification Revision 4.0, September 27, 2017.

This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal

termination enabled, as described by parameter VREFCLK_TERM in Table 6-10, 4-L-PHY SERDES

REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled

before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External

termination should always be enabled on the source side.

Table 6-10. 4-L-PHY SERDES REFCLK Electrical Characteristics

Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N

BALL NUMBERS:E8 / E7

VREFCLK_TERM

Single ended voltage threshold at the reference clock pin when

internal termination is enabled

400

RTERM

Internal termination

62.5

Note

The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver

Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision

1.0 , July 26, 2013.

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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