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rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a

SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.

5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,

analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start

of ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit

errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through

a supply filter.

6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog

supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of

these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains

can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.

7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0

interface is not needed, then domain can be grouped with digital IO 1.8V power rail with power up time

stamp at T1. However, if MMC0 interface is needed, then VDD_MMC0 must not start ramp-up until time

stamp T3 after VDD_CORE has reached VOPR MIN. Any MCU or Main dual voltage IO operating at 1.8V can

be grouped with VDD_MMC0 into a common power rail with power up time stamp T3.

8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,

enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array

domains (VDDAR_xxx) at time stamp T3.

9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry

needing a low noise supply for optimal performance. It is not recommended to combine analog

VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency

switching noise could negatively impact jitter performance of clock, PLL and DLL signals.

10. VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply

for optimal performance. It is not recommended to combine these domains with any other 0.8V domains

since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.

11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch

MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings

into registers during power up sequence.

12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock

frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values.

A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced

depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.

6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing

Figure 6-4 describes the device power-down sequencing.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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