TDA4VM21 datasheet(264/331 Pages) TI

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Table 6-76. MCU_SPI1 IOSET

Signals

IOSET1

IOSET2

BALL NAME

MUX

BALL NAME

MUX

MCU_SPI1_CLK

MCU_SPI1_D0

MCU_SPI1_D1

MCU_SPI1_CS0

MCU_SPI1_CS1

MCU_OSPI1_D1

WKUP_GPIO0_13

MCU_SPI1_CS2

MCU_OSPI1_D2

WKUP_GPIO0_15

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the

device TRM.

6.9.5.19 MMCSD

The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),

and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at

transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking

for syntactical correctness.

For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 sections within

, Signal Descriptions and , Detailed Description.

Note

Some operating modes require software configuration of the MMC DLL delay settings, as shown in

Table 6-77 and Table 6-86.

For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in

the device TRM.

6.9.5.19.1 MMC0 - eMMC Interface

MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the

following eMMC applications:

• Legacy speed

• High speed SDR

• High speed DDR

• HS200

Table 6-77 presents the required DLL software configuration settings for MMC0 timing modes.

Table 6-77. MMC0 DLL Delay Mapping for All Timing Modes

MMCSD0_SS_PHY_CTRL_4_REG

MMCSD0_SS_PHY_CTRL_5_REG

BIT FIELD

[31:24]

[20]

[15:12]

[8]

[4:0]

[17:16]

[10:8]

[2:0]

BIT FIELD NAME

STRBSEL

OTAPDLYENA

OTAPDLYSEL

ITAPDLYENA

ITAPDLYSEL

SELDLYTXCLK

SELDLYRXCLK

FRQSEL

CLKBUFSEL

MODE

DESCRIPTION

STROBE

DELAY

OUTPUT

DELAY

ENABLE

OUTPUT

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DLL/

DELAY CHAIN

SELECT

DLL REF

FREQUENCY

DELAY

BUFFER

DURATION

Legacy

SDR

8-bit PHY

operating 1.8 V,

25 MHz

0x0

0x1

0x10

0x1

0x0

0x7

High

Speed

SDR

8-bit PHY

operating 1.8 V,

50 MHz

0x0

0x1

0xA

0x1

0x0

0x7

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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